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 Freescale Semiconductor
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AN1241
Interfacing the MC68HC705J1A to 9356/9366 EEPROMs
By Mark Glenewinkel CSIC Applications
Freescale Semiconductor, Inc...
INTRODUCTION
This application note describes the hardware and software interface used to communicate between the Freescale MC68HC705J1A MCU and 9356/9366 EEPROM chips. The 93XX series of EEPROMs are an industry standard used widely to store nonvolatile bits of information. The software listing in this application note will work with 9356 and 9366 EEPROMs. The EEPROM bits are arranged in 128 or 256 16-bit registers, respectively. With some modification, the software will work with other 93XX series EEPROMs. Some of the applications in which EEPROMs can be utilized are listed below. * * * * ID number for remote addressing or security Storage of telecommunication information like phone number recall and speed dialing Power down information storage for consumer electronics like TVs and VCRs Reprogrammable calibration data for test/measurement equipment
The 93XX EEPROMs communicate with the outside world using a serial link. Since the MC68HC705J1A does not have the hardware on chip to communicate to the EEPROM, a software driver is used. This method bit programs an I/O port to properly transfer data to and from the EEPROM. A National NM93C56N was used for testing the software routines in this application note.
HARDWARE INTERFACE
The 9356 is a very simple 8-pin device. Appendix A shows a typical connection between the MC68HC705J1A and the 9356. The serial interface connection uses only four pins of the 9356. They are as follows: * * * * CS -- Chip Select SK -- Serial Clock DO -- Serial Data Output DI -- Serial Data Input
These signals must be clocked in a certain way in order to transfer the correct serial data to and from the MC68HC705J1A.
(c)MOTOROLA, INC., 1995
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SOFTWARE INTERFACE
Communication between the MC68HC705J1A and the 9356 is done with a synchronous serial protocol. As mentioned earlier, the MC68HC705J1A bit programs its I/O pins to communicate with the 9356. A timing diagram of the serial link can be found in the 9356 data sheet if needed. The 9356 will accept seven different commands. They are as follows: 1) 2) 3) 4) 5) 6) 7) READ -- WRITE -- WRALL -- ERASE -- ERAL WEN WDS -- -- -- Read a 16-bit data word from an address in memory Write a 16-bit data word from an address in memory Write all addresses with the same 16-bit data word Erase a 16-bit data word from an address in memory Erase all addresses within the memory map Erase/write enable the EEPROM memory Erase/write disable the EEPROM memory
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The 9356 transmission format is a frame of data bits containing an opcode, an address, and if needed, a word of data. The opcode is three bits long, the address is eight bits long, and the data word is 16 bits long. Table 1 illustrates the bit information each instruction needs. Table 1.
Instruction READ WEN ERASE ERAL WRITE WRALL WDS Opcode 110 100 111 100 101 100 100 Address A7-A0 11XXXXXX A7-A0 10XXXXXX A7-A0 01XXXXXX 00XXXXXX D15-D0 D15-D0 Data
IMPLEMENTATION AND TEST
Software was written to provide subroutines to perform each of the seven commands. A total of four bytes of RAM are needed to support the subroutines. These bytes are described below. 1) 2) 3) 4) OP_CODE -- Contains the opcode needed for the command ADDR DATA_H DATA_L -- Contains the address for the command -- The high byte for the data word -- The low byte for the data word
As needed, each EEPROM command subroutine will call other supporting subroutines to execute the transmission of data between the MC68HC705J1A and the 9356. Appendix B contains flowcharts for all of these subroutines.
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Each EEPROM command subroutine has input data and output data. This data is inherent with some commands while others need the information passed to them before the subroutine is called. Table 2 lists the input data needed and output data generated for each of the seven commands.
Table 2:
Command READ EWEN ERASE ERAL Subroutine Input ADDR -- ADDR -- ADDR & DATA_H/L DATA_H/L -- Subroutine Output DATA_H/L -- -- -- -- -- --
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WRITE WRALL EWDS
Code was written and tested with a level of quality equal to the Carnegie-Mellon Software Engineering Institute (SEI) Level 2. A test routine consisting of writing and reading the EEPROM is listed in Appendix C. Refer to Appendix A for the schematic used in the design and test of the software. An LED is used to verify that the test code works properly. The test routine executes the following: 1) 2) 3) 4) 5) 6) 7) 8) Initializes the port on the HC705J1A for serial transmission. LED is turned off. Writes EEPROM address $00 with $AA55. Writes EEPROM address $20 with $1234. Reads EEPROM address $00 and stores it to RAM location TEST1 and TEST2. Reads EEPROM address $20 and stores it to RAM location TEST3 and TEST4. Checks if TEST1 = $AA, TEST2 = $55, TEST3 = $12, and TEST4 = $34. If check is good, then light the LED. If check is bad, do not light the LED. Continue to run in an infinite loop until reset.
For increased reliability, the software watchdog on the MC68HC705J1A is used. Also, a low voltage inhibit circuit, the MC34064, is used to decrease susceptibility to brown out or short power failure conditions.
SUMMARY
This application note has described the interface needed to successfully communicate between the MC68HC705J1A and the 9356. For more information on the MC68HC705J1A, please consult the Technical Data Manual, MC68HC705J1A/D. Contact National Semiconductor or SGS Thompson for technical data on the 93XX series of EEPROM memories. An electronic copy of the code listing in Appendix C and a listing of the test program to fully test all the EEPROM commands can be found on the Freescale MCU BBS. The BBS number is (512) 891-3733. The filename is j1a_9356.arc and is on the CSIC BBS under the APPNOTES directory. Also, Freescale Application Note AN1221/D further details the software and hardware interfaces needed between the 93XX series and other HC05 MCUs.
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APPENDIX A
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HC705J1A to 93C56 Interface
VDD VDD 2 1 9 10 GND VDD 20 RESET IRQ/VPP 19 CHIP_SELECT SERIAL_CLOCK SERIAL_OUT SERIAL_IN --> --> --> <-3 GND U1 VDD VSS C1 0.1uF 1 2 3 4 U2 VCC CS NC SK DI NC DO GND NM93C56N
U3 INPUT RESET GND MC34064
VDD 8 7 6 5 GND VDD X1 CER RES 3 1 2 GND R1 390 D1 LED PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 1 2 18 17 16 15 14 13 12 11
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8 7 6 5 4 3 PB0 PB1 PB2 OSC1 PB3 OSC2 PB4 PB5 MC68HC705J1AP Title
Freescale- CSIC Strategic Applications
HC705J1A -> 93C56 EEPROM Size Document Number A 705J1A.SCH Date: February 1 of 9, 1995 Sheet
REV 1 1
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APPENDIX B
MAIN ROUTINE TEST
INITIALIZE PORT A FOR BIT PROGRAMMING LED IS OFF JSR J9356_EWEN ERASE/WRITE ENABLE THE EEPROM
ADDR = $20
JSR J9356_READ READ DATA FROM EEPROM ADDRESS
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JSR J9356_ERAL ERASE ALL THE EEPROM
TEST3 = DATA_H TEST4 = DATA_L
ADDR = $00 DATA_H = $AA DATA_L = $55
TEST1 = $AA? YES
NO
JSR J9356_WRITE WRITE DATA TO EEPROM ADDRESS
TEST2 = $55? YES
NO
ADDR = $00 DATA_H = $12 DATA_L = $34
JSR J9356_WRITE WRITE DATA TO EEPROM ADDRESS
TEST3 = $12? YES
NO
ADDR = $00
TEST4 = $34? YES
NO
JSR J9356_READ READ DATA FROM EEPROM ADDRESS
LED IS ON TEST PASSED
TEST1 = DATA_H TEST2 = DATA_L
KICK THE WDOG
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J9356_EWDS
J9356_EWEN
J9356_WRITE
J9356_WRAL
OPCODE = $80 ADDR = $00 CS = 1
OPCODE = $80 ADDR = $C0 CS = 1
OPCODE = $A0 CS =1
OPCODE = $80 ADDR = $40 CS = 1
JSR J9356_WR_OP WRITE THE OPCODE
JSR J9356_WR_OP WRITE THE OPCODE
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JSR J9356_WR_ADDR WRITE THE ADDRESS
JSR J9356_WR_ADDR WRITE THE ADDRESS
CS = 0
JSR J9356_WR_DATA WRITE THE DATA
RTS
SER_OUT = 0 CS = 0
JSR J9356_WAIT WAIT UNTIL EEPROM IS READY
RTS
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J9356_ERASE
J9356_ERAL
J9356_READ
OPCODE = $E0 CS =1
OPCODE = $80 ADDR = $80 CS = 1
OPCODE = $C0 CS =1
JSR J9356_WR_OP WRITE THE OPCODE
JSR J9356_WR_OP WRITE THE OPCODE
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JSR J9356_WR_ADDR WRITE THE ADDRESS
JSR J9356_WR_ADDR WRITE THE ADDRESS
CS = 0
CLOCK SER_CLK
JSR J9356_WAIT WAIT UNTIL EEPROM IS READY
JSR J9356_RD_DATA READ THE ADDRESS
RTS
SER_OUT = 0 CS = 0
RTS
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J9356_WR_OP
J9356_WR_ADDR
J9356_WR_DATA
X=3
X=8
X=16
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PUT BIT 7 OF OPCODE ON SER_OUT SHIFT LEFT OPCODE X = X-1
PUT BIT 7 OF OPCODE ON SER_OUT SHIFT LEFT ADDR X = X-1
PUT BIT 7 OF DATA_H ON SER_OUT SHIFT LEFT DATA_L SHIFT LEFT DATA_H X = X-1
NO X = 0? NO X = 0? X = 0? YES YES RTS NO
YES KICK THE WDOG
RTS
RTS J9356_RD_DATA
J9356_WAIT
CS = 1 X=16
READ SER_IN PUT IN C BIT ROTATE LEFT DATA_L ROTATE LEFT DATA_H X = X-1
KICK THE WDOG
EEPROM READY? SER_IN = 0? NO NO
YES
X = 0?
CS = 0
YES
RTS
RTS
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APPENDIX C
***************************************************************************** ***************************************************************************** * * * Main Routine J1A_9356 - 705J1A to 9356 EEPROM * * * ***************************************************************************** * * * File Name: J1A_9356.RTN Copyright (c) Motorola 1995 * * * * Full Functional Description Of Routine Design: * * Program flow: * * Reset: Initializes ports for bit banging. * * Calls EWEN sub to enable write to EEPROM. * * Calls ERAL to erase all EEPROM * * Writes $AA55 to EEPROM $00 * * Writes $1234 to EEPROM $20 * * Reads EEPROM $00 and $20 * * Check for correct data, light LED if correct * * Execute endless loop * * * ***************************************************************************** * * * Part Specific Framework Includes Section * * * ***************************************************************************** #nolist #INCLUDE 'H705J1A.FRK' #list ***************************************************************************** * * * MOR Bytes Definitions for Main Routine * * * ***************************************************************************** org db MOR $21
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;Include the equates for the HC705J1A ;so that all labels can be used.
;COP enabled, osc resistor enabled ;If used on a mask rom part, ; be sure to specify this option.
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***************************************************************************** * * * * Equates and RAM Storage * * * ***************************************************************************** * CS SER_CLK SER_OUT SER_IN equ equ equ equ 0 1 2 3 ;bit ;bit ;bit ;bit # # # # for for for for chip select serial clock serial data out serial data in
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***
RAM storage variables org rmb rmb rmb rmb rmb rmb rmb rmb RAM 1 1 1 1 1 1 1 1
*** ;start of static RAM at $C0 ;command byte ;EEPROM address byte ;MSByte of data ;LSByte of data ;test byte #1 ;test byte #2 ;test byte #3 ;test byte #4
OPCODE ADDR DATA_H DATA_L TEST1 TEST2 TEST3 TEST4
***************************************************************************** * * * * Program Initialization * * * * This section sets up the port for bit banging. * * * * To prevent floating inputs and associated high current draw, * * the HC705J1A has pulldown devices on all I/O pins. This * * initialization should enable these pulldowns on unused I/O * * pins. RESET_ enables the pulldowns, so no code is required. * * * ***************************************************************************** * org lda sta sta lda sta EPROM #$80 PORTA COPR #$87 DDRA
J9356_START
;init portA ; ;kick the wdog ;init i/o of port A
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***************************************************************************** * * * J1A_9356 Main Program Loop * * * * It then runs through the test routine to check for * * proper serial transmission. The LED is lit if the test passes. * * * ***************************************************************************** *** Enable erase/write mode of EEPROM jsr J9356_EWEN ;call ewen routine Erase all EEPROM memory map jsr J9356_ERAL Write $AA55 to $00 lda #$00 sta ADDR lda #$AA sta DATA_H lda #$55 sta DATA_L jsr J9356_WRITE Write $1234 to $20 lda #$20 sta ADDR lda #$12 sta DATA_H lda #$34 sta DATA_L jsr J9356_WRITE Read $00 lda sta jsr lda sta lda sta *** Read $20 lda sta jsr lda sta lda sta #$20 ADDR J9356_READ DATA_H TEST3 DATA_L TEST4 ;load address ;call read routine ;store away data_h to test3 ;store away data_l to test4 #$00 ADDR J9356_READ DATA_H TEST1 DATA_L TEST2 ;load address ;call read routine ;store away data_h to test1 ;store away data_l to test2
***
;call eral routine
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***
;load address ;load data byte high ;load data byte low ;call write routine
***
;load address ;load data byte high ;load data byte low ;call write routine
***
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*** Check results of write and read, light LED if good J9356_CKSUM lda TEST1 ;check test1 cmpa #$AA bne J9356_BRANCH ;branch if no good, no LED lda cmpa bne lda cmpa bne lda cmpa bne bclr TEST2 #$55 J9356_BRANCH TEST3 #$12 J9356_BRANCH TEST4 #$34 J9356_BRANCH 7,PORTA ;check test2 ;branch if no good, no LED ;check test3 ;branch if no good, no LED ;check test4 ;branch if no good, no LED ;EEPROM write and read is good ; light LED
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J9356_BRANCH
clra sta bra
COPR J9356_BRANCH
;kick the wdog
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***************************************************************************** * * * EEPROM Command SubRoutines * * * * These 7 subroutines execute each of the 7 commands * * that the EEPROM will respond to * * * *****************************************************************************
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*** EWEN - subroutine to enable write/erase ****************************** J9356_EWEN lda #$80 ;load opcode sta OPCODE lda #$C0 ;load address sta ADDR bset CS,PORTA ;CS line is high jsr J9356_WR_OP ;write opcode jsr J9356_WR_ADDR ;write address bclr CS,PORTA ;CS line is low rts ;return
*** EWDS - subroutine to disable write/erase ***************************** J9356_EWDS lda #$80 ;load opcode sta OPCODE clr ADDR ;load addr bset CS,PORTA ;CS line is high jsr J9356_WR_OP ;write opcode jsr J9356_WR_ADDR ;write address bclr CS,PORTA ;CS line is low rts ;return
*** WRITE - subroutine to write EEPROM *********************************** J9356_WRITE lda #$A0 ;load opcode sta OPCODE bset CS,PORTA ;CS line is high jsr J9356_WR_OP ;write opcode jsr J9356_WR_ADDR ;write address jsr J9356_WR_DATA ;write data bclr SER_OUT,PORTA bclr CS,PORTA ;CS line is low jsr J9356_WAIT ;wait until EEPROM is ready rts ;return
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*** WRAL - subroutine to write all EEPROM ******************************** J9356_WRAL lda #$80 ;load opcode sta OPCODE lda #$40 ;load addr sta ADDR bset CS,PORTA ;CS line is high jsr J9356_WR_OP ;write opcode jsr J9356_WR_ADDR ;write address jsr J9356_WR_DATA ;write data bclr SER_OUT,PORTA bclr CS,PORTA ;CS line is low jsr J9356_WAIT ;wait until EEPROM is ready rts ;return
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*** READ - subroutine to read EEPROM ************************************* J9356_READ lda #$C0 ;load opcode sta OPCODE bset CS,PORTA ;CS line is high jsr J9356_WR_OP ;write opcode jsr J9356_WR_ADDR ;write address bset SER_CLK,PORTA ;clock the EE bclr SER_CLK,PORTA jsr J9356_RD_DATA ;read data bclr SER_OUT,PORTA bclr CS,PORTA ;CS line is low rts ;return
*** ERASE - subroutine to erase EEPROM *********************************** J9356_ERASE lda #$E0 ;load opcode sta OPCODE bset CS,PORTA ;CS line is high jsr J9356_WR_OP ;write opcode jsr J9356_WR_ADDR ;write address bclr CS,PORTA ;CS line is low jsr J9356_WAIT ;wait until EEPROM is ready rts
*** ERAL - subroutine to erase all EEPROM ******************************** J9356_ERAL lda #$80 ;load opcode and addr sta OPCODE sta ADDR bset CS,PORTA ;CS line is high jsr J9356_WR_OP ;write opcode jsr J9356_WR_ADDR ;write address bclr CS,PORTA ;CS line is low jsr J9356_WAIT ;wait until EEPROM is ready rts
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***************************************************************************** * * * EEPROM Supporting SubRoutines * * * * These subroutines support the functions called from the Command subs * * * ***************************************************************************** *** Subroutine to write 3 bit opcode ************************************ J9356_WR_OP ldx #3T ;init counter for LOOP1 * Write to the serial output pin J9356_LOOP1 brclr 7,OPCODE,J9356_L1_2 ;if opcode bit7 = 0, goto L1_2 bset SER_OUT,PORTA ;ser_out = 1 bra J9356_L1_3 ;goto L1_3 J9356_L1_2 bclr SER_OUT,PORTA ;ser_out = 0 * Clock the serial clock pin J9356_L1_3 bset SER_CLK,PORTA bclr SER_CLK,PORTA asl OPCODE decx bne J9356_LOOP1 clra sta COPR rts
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;ser_clk = 1 ;ser_clk = 0 ;rotate the opcode ;decrease counter loop ;is LOOP1 finished? ;kick the wdog ;return
*** Subroutine to write 8 bit address **************************************** J9356_WR_ADDR ldx #8T ;init counter for LOOP2 * Write to the serial output pin J9356_LOOP2 brclr 7,ADDR,J9356_L2_2 ;if addr bit7 = 0, goto L2_2 bset SER_OUT,PORTA ;ser_out = 1 bra J9356_L2_3 ;goto L2_3 J9356_L2_2 bclr SER_OUT,PORTA ;ser_out = 0 * Clock the serial clock pin J9356_L2_3 bset SER_CLK,PORTA bclr SER_CLK,PORTA asl ADDR decx bne J9356_LOOP2 rts
;ser_clk = 1 ;ser_clk = 0 ;rotate the addr ;decrease counter loop ;is LOOP2 finished? ;return
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*** Subroutine to write 16 bit data ****************************************** J9356_WR_DATA ldx #16T ;init counter for LOOP4 * Write the serial output pin with data J9356_LOOP4 brclr 7,DATA_H,J9356_L4_2 ;if addr bit7 = 0, goto L4_2 bset SER_OUT,PORTA ;ser_out = 1 bra J9356_L4_3 ;goto L4_3 J9356_L4_2 bclr SER_OUT,PORTA ;ser_out = 0 * Clock the serial clock pin J9356_L4_3 bset SER_CLK,PORTA bclr SER_CLK,PORTA asl DATA_L rol DATA_H decx bne J9356_LOOP4 rts
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;ser_clk = 1 ;ser_clk = 0 ;rotate the DATA_L ;rotate the DATA_H ;decrease counter loop ;is LOOP4 finished? ;return
*** Subroutine to read 16 bit data *************************************** J9356_RD_DATA ldx #16T ;init counter for LOOP3 * Read the serial J9356_LOOP3 brclr J9356_L3 rol rol * input pin SER_IN,PORTA,J9356_L3 ;carry bit = serial in DATA_L ;rotate left result DATA_H
Clock the serial clock pin bset SER_CLK,PORTA bclr SER_CLK,PORTA decx bne J9356_LOOP3 rts
;ser_clk = 1 ;ser_clk = 0 ;decrease counter loop ;is LOOP3 finished? ;return
* Wait until write cycle is over J9356_WAIT bset CS,PORTA ;CS line is high J9356_W2 clra sta COPR ;kick the wdog brclr SER_IN,PORTA,J9356_W2 bclr CS,PORTA ;CS line is low rts ;return
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***************************************************************************** * * * Interrupt and Reset vectors for Main Routine * * * ***************************************************************************** org fdb RESET J9356_START
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NOTES
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NOTES
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Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part.
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